Physical L1

Classical Controller Area Network with 11-bit and 29-bit identifiers, CSMA/CR arbitration, and up to 8 data bytes. Dominant/recessive wir…

CAN Flexible Data-Rate extends classical CAN with up to 64 data bytes and a faster data-phase bitrate after arbitration. BRS and ESI bits…

Asynchronous character framing with start bit, 5–9 data bits, optional parity, and one or two stop bits. RS-232 defines voltage levels an…

Two-wire multi-master bus (SCL/SDA) with open-drain wired-AND, 7/10-bit addressing, and ACK bits after every byte. Start/stop conditions …

Full-duplex synchronous bus with SCLK, MOSI, MISO, and per-device chip select. Mode is defined by CPOL/CPHA (or mode 0–3); there is no st…

ARM two-pin debug protocol (SWDIO/SWCLK) replacing full JTAG for Cortex-M. Packets select DP/AP registers for memory access, breakpoints,…

Binary Modbus ADU on serial lines: address, PDU (function + data), and CRC-16. Silent intervals of 3.5 character times delimit frames; fu…

Primary Rate ISDN: T1 23B+D or E1 30B+D with a 64 kb/s D-channel for Q.931/LAPD. Timeslots map B-channels; framing and line coding come f…

Lossless switched fabric with its own L2/L3 (LID/GID), subnet manager, and verbs transport (RC/UD/…). Credits, VLs, and partition keys pr…

Ubiquitous LAN frame: 6-byte MACs, 2-byte EtherType, payload, and 32-bit FCS. Preamble/SFD precede the frame on the wire; 802.1Q inserts …

Differential multi-drop serial physical layer used under Modbus RTU, Profibus, and many industrial buses. Half-duplex pairs need directio…

Low-cost single-master UART-based vehicle bus for body electronics. Schedule tables, break/sync/ID framing, and enhanced checksum define …

Boundary-scan and debug TAP with TMS/TCK/TDI/TDO state machine. Chains, IR/DR lengths, and adaptive clocking matter when probing multi-ch…

Single-wire half-duplex bus with parasite power for sensors and ID chips. Presence pulse, ROM commands, and strict slot timing are the us…

I²C-derived management bus with timeouts, PEC, and defined commands for power/thermal devices. Stricter electrical and timing rules than …

SPI variant with 1/2/4 IO lines for flash and peripherals. Address/command phases and dummy cycles dominate throughput; mode and DDR opti…

ARM Cortex single-pin async trace for printf-style ITM packets and event counters. Baud must match debugger; Manchester vs UART encoding …

Single-edge nibble transmission for automotive sensors. Tick time, sync pulse, and CRC nibble framing are fixed; Fast/Slow channels carry…

Timed pulse encodings for actuators, RC control, and sensing. Duty cycle, period stability, and edge polarity define the information chan…

Management interface for Ethernet PHYs: MDC clock plus bidirectional MDIO with preamble, start, op, PHYAD, and REGAD fields. Clause 22 ex…

SD card command/response/data protocol extended so non-memory functions (Wi-Fi, GPS, Bluetooth) enumerate as SDIO devices. CMD/DAT lines,…

Time-triggered dual-channel automotive network with static TDMA and dynamic mini-slot segments inside a communication cycle. Sync frames …

Ring-topology multimedia network historically used for in-vehicle audio, video, and control. Synchronous, packet, and control channels sh…

Single-pair Ethernet PHYs (OPEN Alliance / IEEE 802.3bw/bp and successors) built for vehicle harnesses, often with TSN for latency and sh…

Token-passing RS-485 fieldbus from PI for DP masters and slaves in factory automation. Baud rate, station addresses, and GSD device descr…

Lighting-control bus (IEC 62386) with Manchester encoding, short addresses, and group/scene concepts. Forward frames command ballasts and…

Short-range low-power radio using advertising, connections, and GATT attribute tables for application data. PHY rates (1M/2M/Coded), ATT …

LPWAN MAC over LoRa chirp spread-spectrum PHY with OTAA/ABP join, session keys, and adaptive data rate. Uplink/downlink windows, duty-cyc…

Nordic Semiconductor short-range proprietary packet modes, including Enhanced ShockBurst, for low-latency links on nRF radios. Address fi…

Host-centric shared bus with control, bulk, interrupt, and isochronous transfers at low/full/high speed. Device identity lives in descrip…

ASCII talker sentence protocol for GNSS and marine instruments, traditionally over 4800 8N1 serial (higher rates are common now). Sentenc…

ISDN Basic Rate Interface providing two 64 kb/s B-channels plus a 16 kb/s D-channel for Q.931 signaling (2B+D). S/T and U interfaces diff…

Channel Associated Signaling and MFC-R2 multi-frequency compelled trunk signaling used on legacy TDM interconnects. Line signaling may be…

Time-division multiplexed digital trunks such as T1 (24×DS0) and E1 (32 timeslots) framed per G.704 and related recommendations. Framing,…

Digital Mobile Radio — an ETSI TDMA LMR standard with two slots in a 12.5 kHz channel for voice, data, and trunking control. Tier I/II/II…

APCO Project 25 public-safety digital radio with FDMA Phase 1 and TDMA Phase 2 common air interfaces. IMBE/AMBE vocoders, trunking contro…

NVIDIA high-bandwidth GPU interconnect for peer-to-peer and coherent-ish memory traffic inside a node or NVSwitch domain. Generations dif…

Compute Express Link — a cache-coherent interconnect riding PCIe PHY for memory expanders and accelerators. .io, .cache, and .mem protoco…

Universal Chiplet Interconnect Express — a die-to-die standard with streaming and protocol mappings (including PCIe/CXL). Advanced packag…

PCI Express — packetized serial I/O with lanes, LTSSM link training, and TLP/DLLP layers. Gen5/Gen6 rates and retimers define reach; ACS …

IEEE 802.11 wireless LAN using CSMA/CA with management, control, and data frames plus WPA-family security. PHY generations (n/ac/ax/be) c…

BR/EDR Bluetooth forming piconets for audio and serial profiles such as A2DP, HFP, and SPP. Frequency hopping and ACL/SCO/eSCO logical li…

Serial ATA disk interconnect using FIS frames and typically an AHCI host interface. Link speed negotiation and Native Command Queuing def…

Musical Instrument Digital Interface — real-time music control messages (note on/off, CC, program change) over 5-pin DIN, USB, or RTP-MID…

DMX512 lighting/show-control bus: 250 kb/s RS-485 carrying a break, mark-after-break, start code, and up to 512 channel slots. Controller…