ProtoLab
Probe the wire. Learn the frame.
History, wire decodes, and virtual labs for embedded buses, telephony, and AI fabrics — bit timing to stack maps.
Deep labs
Ready to probe
Howto, history, wire decodes, and interactive labs across 139 protocols.
CAN 2.0B
Lab readyClassical Controller Area Network with 11-bit and 29-bit identifiers, CSMA/CR arbitration, and up to 8 data bytes. Dominant/recessive wir…
CAN FD
Lab readyCAN Flexible Data-Rate extends classical CAN with up to 64 data bytes and a faster data-phase bitrate after arbitration. BRS and ESI bits…
UART / RS-232
Lab readyAsynchronous character framing with start bit, 5–9 data bits, optional parity, and one or two stop bits. RS-232 defines voltage levels an…
I²C
Lab readyTwo-wire multi-master bus (SCL/SDA) with open-drain wired-AND, 7/10-bit addressing, and ACK bits after every byte. Start/stop conditions …
SPI
Lab readyFull-duplex synchronous bus with SCLK, MOSI, MISO, and per-device chip select. Mode is defined by CPOL/CPHA (or mode 0–3); there is no st…
SWD
Lab readyARM two-pin debug protocol (SWDIO/SWCLK) replacing full JTAG for Cortex-M. Packets select DP/AP registers for memory access, breakpoints,…
Domains
Pick a stack
Embedded pins, telephony signaling, and AI fabrics — each with its own stack map.
Graph
See the connections
Force graph of protocols across layers and domains — then jump straight into a lab.