Protocol
I²C
I2C · TWI · Inter-Integrated Circuit
Two-wire multi-master bus (SCL/SDA) with open-drain wired-AND, 7/10-bit addressing, and ACK bits after every byte. Start/stop conditions and clock stretching define transaction boundaries.
Tags
open-drainackmulti-masterembedded
Sources
- NXP UM10204 I²C-bus specification
- SMBus 3.x (timeouts / PEC)
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