PCI Express

1. 1

   Queue pair

   Host allocates submission/completion queues in shared memory.

2. 2

   Build command

   Opcode, NSID, PRP/SGL point at the buffer.

3. 3

   Doorbell

   Host writes SQ tail doorbell; controller fetches the command.

4. 4

   DMA data

   Controller moves payload via PCIe (or RDMA for NVMe-oF).

5. 5

   Completion

   CQ entry + interrupt/MSI-X; host advances CQ head.

Step 1 / 5

PCI Express fields